1. Field of the Invention
The present invention relates to a driving circuit for driving an electro-optical panel that is free from image quality degradation due to noise, a driving method for driving the electro-optical panel, an electro-optical device, and electronic equipment.
2. Description of the Related Art
Conventional electro-optical devices, such as an active-matrix type liquid-crystal display device, include a liquid-crystal panel and a video processing circuit. The liquid-crystal panel is mainly formed of an element substrate having a matrix of pixel electrodes arranged thereon, a counter substrate having a counter electrode and a color filter arranged thereon, and a liquid crystal encapsulated between the two substrates.
A pixel electrode is arranged at an intersection of a scanning line and a data line, and is connected to a switching element such as a transistor. When a selection signal is applied to a switching element through a scanning line, the switching element becomes conductive. When a video signal is applied to the pixel electrode through the data line during the conductive state of the switching element, a charge responsive to a voltage of the video signal is stored in the liquid crystal layer between the pixel electrode and the counter electrode. When the switching element is turned off subsequent to the storage of charge, the charge is maintained in the liquid crystal layer if the resistance of the liquid crystal layer is high enough. If the amount of charge stored is controlled by driving each switching element, the liquid crystal changes the alignment state thereof from pixel to pixel, and required information is thus presented.
It suffices to store charge in the liquid crystal layer in each pixel during a portion of the time. First, a scanning line driving circuit successively selects scanning lines one by one. Second, a data line driving circuit outputs a sampling signal (pulse) to successively select one or a plurality of data lines at a time. Third, a video signal fed through a video signal line is sampled in response to the sampling signal, and is then fed to a corresponding data line. In this way, time-division multiplex driving is performed in which scanning lines and data lines are shared by a plurality of pixels.
If the sampling signals (pulses), which need to be output in an exclusive manner, overlaps each other in the output thereof for any reason, a video signal which is intended for a given data line happens to be sampled for an adjacent data line. Image quality is thus degraded. To resolve such an image degradation, a so-called enable circuit is arranged in an output stage of the data line driving circuit so that the pulse width of the sampling signal is narrowed to the pulse width of the enable pulse. The enable circuit prevents consecutive sampling signals from overlapping each other in time.
A video signal processor circuit generates a video signal by performing processes, such as a gamma correction and an amplification and inversion process, on an input video signal. The video signal processor and the liquid-crystal panel are connected to each other through an FPC (Flexible Printed Circuit), and the video signal is thus sent to the liquid-crystal panel through the FPC.
Since the pitch of wiring becomes finer in the liquid-crystal panel and the operation frequency of the liquid-crystal panel becomes higher along with a higher definition of a display screen, the delay of an enable pulse with respect to a video signal becomes a problem. The liquid-crystal panel is supplied with the enable signal, etc., via signal lines formed on a glass substrate. Since parasitic capacitance and resistance on the glass substrate are higher than those in the FPC, the liquid-crystal panel is subject to signal delay.
The enable pulse must be supplied in synchronization with the video signal. In the liquid-crystal panel, the supply route of the enable pulse and the supply route of the video signal are different. Even if the enable pulse synchronized with the video signal is fed to the liquid-crystal panel, therefore, the enable pulse is out of phase with the video signal in the liquid-crystal panel. The problem arises with a sampling signal for appropriately sampling the video signal.
The liquid-crystal panel is typically controlled by a variety of timing signals obtained through the digital process. The timing signal, which is a digital signal, includes a high-frequency component, and is synchronized with the video signal. For this reason, the timing signal contains a large amount of high-frequency components at the rising edge thereof and the falling edge thereof. Noise synchronized with the level shifting of the timing signal overlaps an analog video signal.
If noise is superimposed on the video signal, a voltage different from the original component thereof is sampled, and applied to the pixel electrode. Superimposed noise is then recognized as a vertical streak, thereby degrading image quality. Along with a compact design of the device, a step of controlling noise is an urgent need in view of a high-density circuit substrate and FPC substrate.
The present invention has been developed in view of the above problem, and it is an object of the present invention to provide a driving circuit for driving an electro-optical panel which generates an appropriate sampling signal and is free from degradation in image quality even if an enable pulse is out of phase with a video signal and even if noise is superimposed on the video signal, and to provide a method for driving the electro-optical panel, an electro-optical device, and electronic equipment.
A driving circuit of the present invention for driving an electro-optical panel having a transistor and a pixel electrode at each intersection of each of a plurality of scanning lines and each of a plurality of data lines, includes a scanning line driving circuit which selects a scanning line to supply a transistor corresponding to the selected scanning line with a signal to turn on the transistor, a data line driving circuit which generates a shift pulse to select a data line within a duration during which the scanning line is selected, and limits the pulse width of the shift pulse to the pulse width of an enable pulse narrower than the shift pulse width and outputs the shift pulse with the narrow pulse width as a sampling signal, a sampling circuit which samples a video signal within the pulse duration of the sampling signal and feeds the sampled signal to at least one data line, a dummy circuit which is arranged adjacent to the sampling circuit and the data line driving circuit, and outputs a phase difference signal representing a phase difference between a monitor signal supplied in synchronization with the video signal and a reference pulse supplied in synchronization with the enable pulse, and an enable pulse adjustment circuit which adjusts the phase of the enable pulse so that the phase of the enable pulse leads with respect to the video signal when the phase difference signal indicates that the reference pulse lags the monitor signal in phase, or so that the phase of the enable pulse lags with respect to the video signal when the phase difference signal indicates that the reference pulse leads the monitor signal in phase. When the reference signal synchronized with the enable pulse is delayed with respect to the monitor signal in this arrangement, the phase of the enable pulse is adjusted to cancel out the delay.
In the above driving circuit, the dummy circuit preferably includes an element identical to that which is also used in the sampling circuit and the data line driving circuit as portions thereof. In this arrangement, the delay occurring in the supply route of the enable pulse is accurately simulated.
Preferably, in the above driving circuit, the enable pulse adjustment circuit repeatedly alternates between delaying and advancing the enable pulse in phase within a predetermined range with respect to a target value. Since the phase of the enable signal fluctuates with respect to the target value in this arrangement, the phase of the sampling signal fluctuates accordingly. If the sampling signal fluctuates, noise is sampled sometimes, and is not sampled at other times. Noise is thus distributed on a screen, becoming less visible. The present invention prevents the quality of image for being degraded.
Preferably in the above driving circuit, the scanning line driving circuit, the data line driving circuit, the sampling circuit, and the dummy circuit are arranged on the same substrate.
Preferably, the driving circuit further includes a determining circuit which determines whether a constant duration of time elapses from the switching of power source, or determines whether a change in temperature of the electro-optical panel falls within a predetermined value, wherein the enable pulse adjustment circuit adjusts the phase of the enable pulse until the determination results provided by the determining circuit become affirmative, and when the determination results provided by the determining circuit become affirmative, the enable pulse adjustment circuit fixes the phase of the enable pulse to a phase immediately prior to the occurrence of the affirmative results. In this arrangement, the phase of the enable pulse is adjusted under certain conditions only.
Preferably in the driving circuit, the enable pulse adjustment circuit includes a group of delay circuits which outputs a plurality of signals different from each other in the amount of delay by delaying the reference clock signal synchronized with the video signal, a selection signal generator circuit which generates a selection signal to select one from among the plurality of signals output from the group of delay circuits, in accordance with the phase difference represented by the phase difference signal, a selector circuit which selects the one of the signals represented by the selection signals, from among the plurality of signals output from the group of delay circuits, as an enable clock signal, and an enable signal generator circuit which generates the enable pulse from a portion of the enable clock signal. In this arrangement, the phase of the enable pulse is adjusted by selecting one of the plurality of signals that are obtained by delaying the reference clock signal.
Preferably in the driving circuit, the selection signal generator circuit preferably generates the selection signal based on the results of comparison of the phase difference represented by the phase difference signal, namely, the phase lag of the reference pulse with respect to the monitor signal, with a predetermined target time. In this arrangement, the phase delay of the enable pulse with respect to the video signal is controlled to the target time.
In the driving circuit, the selection signal generator circuit preferably generates the selection signal every horizontal scanning period or every plurality of horizontal scanning periods. In this arrangement, the phase of the enable pulse is adjusted every horizontal scanning period or every plurality of horizontal scanning periods.
Preferably in the driving circuit, the phase difference signal is a pulse signal, the pulse width of which becomes shorter as the delay of the reference pulse becomes longer with respect to the monitor signal, the enable pulse adjustment circuit further includes a comparator circuit which compares the pulse width of the phase difference signal with a predetermined target time to determine which is longer, and the selection signal generator circuit generates the selection signal based on the comparison results provided by the comparator circuit, In this arrangement, the phase of the enable pulse is accurately adjusted.
Preferably in the driving circuit, the phase difference signal is a pulse signal, the pulse width of which becomes shorter as the delay of the reference pulse becomes longer with respect to the monitor signal, the group of delay circuits is composed of a plurality of delay circuits, each having a respective delay amount, connected in cascade, the enable pulse adjustment circuit further includes a comparator circuit which compares the pulse width of the phase difference signal with a predetermined target time to determine which is longer, and the selection signal generator circuit generates the selection signal for selecting a signal having a delay amount one notch longer from among the plurality of signals output from the group of delay circuits when the comparison results provided by the comparator circuit are affirmative, or generates the selection signal for selecting a signal having a delay amount one notch shorter from among the plurality of signals output from the group of delay circuits when the comparison results provided by the comparator circuit are non-affirmative. In this arrangement, the amount of delay of the enable pulse with respect to the monitor signal gradually becomes closer to the target time.
Preferably in the driving circuit, the enable pulse adjustment circuit further includes an adder which adds disturbance to the selection signal generated by the selection signal generator circuit, and the selector circuit selects a signal indicated by the selection signal to which disturbance is added by the adder, from among the plurality of signals output from the group of delay circuits. In this arrangement, the phase of the enable pulse fluctuates due to disturbance.
Preferably in the driving circuit, the selection signal generator circuit generates the selection signal for selecting a signal having a longer phase delay from among the plurality of signals output from the group of delay circuits when the phase difference represented by the phase difference signal, namely, the phase delay of the reference pulse with respect it the monitor signal falls within a constant value. In this arrangement, the phase of the enable pulse is forced to fluctuate.
Preferably in the driving circuit, the phase difference signal is a pulse signal, the pulse width of which becomes shorter as the delay of the reference pulse becomes longer with respect to the monitor signal, the group of delay circuits is composed of a plurality of delay circuits, each having a respective delay amount, connected in cascade, the enable pulse adjustment circuit further includes a comparator circuit which compares the pulse width of the phase difference signal with a predetermined target time to determine which is longer, and the selection signal generator circuit includes a detector circuit which detects whether or not previous comparison results provided by the comparator circuit coincide with current comparison results provided by the comparator circuit, and in case of coincident detection results between the previous and current comparison results, the selection signal generator circuit generates a selection signal for selecting a signal having a delay amount one notch longer from among the plurality of signals output from the group of delay circuits when the current comparison results are affirmative, or generates a selection signal for selecting a signal having a delay amount one notch shorter from among the plurality of signals output from the group of delay circuits when the current comparison results are not affirmative, or in case of non-coincident detection results between the previous and current comparison results, the selection signal generator circuit generates a selection signal for selecting a signal having a delay amount several notches longer from among the plurality of signals output from the group of delay circuits when the current comparison results are affirmative, or generates a selection signal for selecting a signal having a delay amount several notches shorter from among the plurality of signals output from the group of delay circuits when the current comparison results are not affirmative. This arrangement detects a change in a magnitude relationship, such as a change from phase lag to phase lead or a change from phase lead to phase lag. When a change is detected in the phase relation, the phase of the enable pulse is increased.
Preferably in the driving circuit, the data line driving circuit generates a shift pulse by shifting a start pulse fed during a blanking time in a horizontal scanning period in response to a clock signal controlling a shifting operation, and furthermore, the data line driving circuit includes a start pulse adjustment circuit which adjusts the phase of the start pulse in the same direction in and by substantially the same amount by which the phase of the enable pulse is adjusted by the enable pulse adjustment circuit, and a clock signal adjustment circuit which adjusts the phase of the clock signal in the same direction in and by substantially the same amount by which the phase of the enable pulse is adjusted by the enable pulse adjustment circuit. In this arrangement, not only the phase of the enable pulse but also the phases of the start pulse and the clock signal are equally adjusted.
In the arrangement in which both the start pulse and the clock signal are adjusted in phase, the start pulse is preferably used as the reference pulse. This arrangement eliminates the need for generating a new reference pulse. When the dummy circuit outputs the phase difference signal representing the phase difference between the start pulse supplied during a horizontal scanning period and the monitor signal, preferably the start pulse adjustment circuit adjusts the phase of the start pulse, based on the phase difference signal, during a horizontal scanning period after the first horizontal scanning period.
An electro-optical device of the present invention includes an electro-optical panel and a timing control circuit. The electro-optical panel includes a transistor at each intersection of each of a plurality of scanning lines and each of a plurality of data lines, a pixel electrode arranged corresponding to the transistor, a scanning line driving circuit which selects a scanning line to supply a transistor corresponding to the selected scanning line with a signal to turn on the transistor, a data line driving circuit which generates a shift pulse to select a data line, and limits the pulse width of the shift pulse to the pulse width of an enable pulse narrower than the shift pulse width and outputs the shift pulse with the narrow pulse width as a sampling signal, a sampling circuit which samples a video signal within the pulse duration of the sampling signal within a duration during which the scanning line is selected and feeds the sampled signal to one data line, a dummy circuit which is arranged adjacent to the sampling circuit and the data line driving circuit, and outputs a phase difference signal representing a phase difference between a monitor signal supplied in synchronization with the video signal and a reference pulse supplied in synchronization with the enable pulse. The timing control circuit includes an enable pulse adjustment circuit which adjusts the phase of the enable pulse so that the phase of the enable pulse leads with respect to the video signal when the phase difference signal indicates that the reference pulse lags the monitor signal in phase, or so that the phase of the enable pulse lags with respect to the video signal when the phase difference signal indicates that the reference pulse leads the monitor signal in phase. In this arrangement, as in the driving circuit, the phase of the enable pulse is adjusted to cancel a delay when the reference pulse synchronized with the enable pulse is delayed with respect to the monitor signal.
Preferably in the electro-optical device, in the electro-optical panel, the data lines are grouped into blocks, each block having n lines (n is an integer equal to or larger than 2), the video signal is divided into n signals, which are respectively fed to n video signal lines in parallel, and the sampling circuit samples the n video signals supplied in parallel to the n video signal lines in response to one sampling signal, and then feeds the sampled signals to a data lines on a one to one basis. In comparison with a construction in which a video signal is sampled to one video signal line by one sampling signal, this arrangement assures sufficient time for a sample and hold process and a discharge process.
Electronic equipment of the present invention includes one of the above-referenced electro-optical devices and presents an image. For example, the electronic equipment of the present invention may be a video projector, a mobile personal computer, a pager, a mobile telephone, a television, a view-finder type or a direct-monitoring type video camera, a car navigation device, a PDA, or the like.
A driving method of the present invention for driving an electro-optical panel having a transistor and a pixel electrode at each intersection of each of a plurality of scanning lines and each of a plurality of data lines, includes the steps of selecting a scanning line to supply a transistor corresponding to the selected scanning line with a signal to turn on the transistor, generating a shift pulse to select a data line within a duration during which the scanning line is selected and limiting the pulse width of the shift pulse to the pulse width of an enable pulse narrower than the shift pulse width and outputting the shift pulse with the narrow pulse width as a sampling signal, sampling a video signal within the pulse duration of the sampling signal and feeding the sampled signal to at least one data line, outputting a phase difference signal representing a phase difference between a monitor signal supplied in synchronization with the video signal and a reference pulse supplied in synchronization with the enable pulse, and adjusting the phase of the enable pulse so that the phase of the enable pulse leads with respect to the video signal when the phase difference signal indicates that the reference pulse lags the monitor signal in phase, or so that the phase of the enable pulse lags with respect to the video signal when the phase difference signal indicates that the reference pulse leads the monitor signal in phase. In this arrangement, as in the driving circuit and the electro-optical device, the phase of the enable pulse is adjusted to cancel a delay when the reference pulse synchronized with the enable pulse is delayed with respect to the monitor signal.
The driving method preferably includes the steps of outputting a plurality of signals different from each other in the amount of delay by delaying the reference clock signal synchronized with the video signal, generating a selection signal to select one from among the plurality of signals output from the group of delay circuits, in accordance with the phase difference represented by the phase difference signal, selecting the one of the signals represented by the selection signals, from among the plurality of signals output from the group of delay circuits, as an enable clock signal, and generating the enable pulse from a portion of the enable clock signal to adjust the enable pulse. In this method, the phase of the enable pulse is adjusted by selecting one of the plurality of signals that are obtained by delaying the reference clock signal.
Preferably in the driving method, the phase difference signal is a pulse signal, the pulse width of which becomes shorter as the delay of the reference pulse becomes longer with respect to the monitor signal. The driving method preferably includes the steps of comparing the pulse width of the phase difference signal with a predetermined target time to determine which is longer, and generating a selection signal for selecting a signal having a delay amount one notch longer from among the plurality of signals output from the group of delay circuits when the comparison results; are affirmative, or generating a selection signal for selecting a signal having a delay amount one notch shorter from among the plurality of signals output from the group of delay circuits when the comparison results are non-affirmative. In this method, the amount of delay of the enable pulse with respect to the monitor signal gradually becomes closer to the target time.
The driving method preferably includes the steps of adding disturbance to the generated selection signal, and selecting a signal indicated by the selection signal to which disturbance is added, from among the plurality of signals output from the group of delay circuits to adjust the enable pulse. In this method, the phase of the enable pulse is forced to fluctuate.
The driving method preferably includes a stop of generating the selection signal for selecting a signal having a longer phase delay from among the plurality of signals output from the group of delay circuits when the phase difference represented by the phase difference signal, namely, the phase delay of the reference pulse with respect to the monitor signal falls within a constant value. In this method, the phase of the enable pulse is forced to fluctuate.
In the driving method, the phase difference signal is a pulse signal, the pulse width of which becomes shorter as the delay of the reference pulse becomes longer with respect to the monitor signal. The driving method preferably includes the steps of comparing the pulse width of the phase difference signal with a predetermined target time to determine which is longer, and detecting whether or not previous comparison results coincide with current comparison results, and in case of coincident detection results between the previous and current comparison results, generating a selection signal for selecting a signal having a delay amount one notch longer from among the plurality of signals output from the group of delay circuits when the current comparison results are affirmative, or generating a selection signal for selecting a signal having a delay amount one notch shorter from among the plurality of signals output from the group of delay circuit when the current comparison results are not affirmative, or in case of non-coincident detection results between the previous and current comparison results, generating a selection signal for selecting a signal having a delay amount several notches longer from among the plurality of signals output from the group of delay circuits when the current comparison results are affirmative, or generating a selection signal for selecting a signal having a delay amount several notches shorter from among the plurality of signals output from the group of delay circuits when the current comparison results are not affirmative. This method detects an inversion in a magnitude relationship, such as a change from phase lag to phase lead or a change from phase lead to phase lag. When a change is detected in the phase relation, the phase of the enable pulse is increased.